Features

PLECS PIL (PROCESSOR-IN-LOOP)

The PLECS PIL package is a complete solution for Processor-In-the-Loop (PIL) simulations with PLECS Standalone or PLECS Blockset. With PLECS PIL you can execute control code on actual embedded hardware tied into the virtual loop of a PLECS model.

Why PIL?

Engineers developing embedded control algorithms often test such code, or portions thereof, by executing it inside a circuit simulator. Using PLECS, this can be easily done with a C-Script or DLL block.

The PIL approach, on the other hand, executes the control algorithms on the real embedded hardware. Instead of reading the actual sensors of the power converter, values calculated by the simulation tool are used as inputs to the embedded algorithm. Similarly, outputs of the control algorithms executing on the processor are being fed back into the simulation to drive the virtual environment.

This detects platform-specific software defects such as overflow conditions and casting errors. Also, although PIL testing does not execute the control algorithms in true real-time, the control tasks do execute at the normal rate between two simulation steps. Therefore, PIL simulation can be used to expose and analyze potential problems related to the multi-threaded execution of control algorithms, including jitter and resource corruption.

Run your Processor in the Loop

The PLECS PIL package is a complete solution for Processor-In-the-Loop (PIL) simulations with PLECS Standalone or PLECS Blockset.

With PLECS PIL you can execute control code on actual embedded hardware tied into the virtual loop of a PLECS model.

Supported Embedded Processors

1. TI C2000 Family (including latest Delfino dual-core processors)

2. ST STM32F4 Series

3. Microchip dsPIC33F ( MC version)